WHOLE NEW NVM TECHNOLOGY
The conventional FPGA is constructed with SRAM devices for Look-Up-Table (LUT) in Logic Elements (LEs) and circuit interconnection matrixes. Digital circuits are configured by storing digital bits in the SRAM devices of the LUTs and interconnection matrix in FPGA. The configuration of digital circuits using convectional FPGA must be loaded from a non-volatile storage device owing to the volatility of SRAM after chip power off. All the configuration data have to be loaded completely before enabling the digital circuits. The data loading process is the major bottleneck for the initialization of the configured digital circuit device. The important function of on-chip modification for digital circuit development is also hindered by the whole configuration data loading process. The circuit initialization speed and the on-chip modification capability for configurable digital circuitries can be dramatically improved by using non-volatile memory in the LUTs and interconnection matrix. We have applied the LGNVM devices to replace the SRAM devices in LUTs and interconnection matrixes to form Non-Volatile Field Programmable Gate Array (NV-FPGA).
NV-FPGA (Non-Volatile Field Programmable Gate Array)
An N-bit LUT in FPGA configured for a combination logic function contains 2N SRAM cell devices and an N-bit input de-multiplex switches for accessing the SRAM data. As shown in Fig. 1 the non-volatile LUT is constructed by substituting a bit of SRAM cell device with a pair of complementary LGNVM devices. The pair of complementary LGNVM devices are configured into a bit by programming one device to the high threshold voltage state and the other device remaining at the low threshold voltage state.
By applying VDD and VSS voltage biases to the two input nodes respectively, and a control gate voltage bias between the high/low threshold voltages to the control gate, the voltages at the output nodes of the complementary pair are either VDD (“1”) or VSS (“0”). Thus the 2N configured non-volatile bits of the complementary pairs in the N-bit NV-LUT can be accessed by activating the N-bit de-multiplex switches. The digital data at the output of the NV-LUT are then captured in a data flip-flop of the logic element for further digital circuit processing.
The interconnection matrixes are applied to connect the logic elements to form a digital circuit in FPGA. The Configurable Interconnection Matrix (CIM) in NV-FPGA is constructed by a LGNVM array with M-input bus line node and 2N-switching output nodes and one M straight amplified output nodes as shown in Fig. 2. The M x N LGNVM device array in the CIM are initially erased to the low threshold voltage state. Consequently the crossed-LGNVM devices as the cross-bar switches are all “on” to connect the M vertical lines with the N horizontal lines by applying a control voltage bias between the low/high threshold voltages.
To configure the CIM, the crossed-LGNVM devices at the intersections of the vertical lines and horizontal lines are programmed to high voltage state to disconnect the nodes between vertical lines and horizontal lines. After configuration the CIM is activated by applying a voltage bias between the high/low threshold voltages to the control gates of the M x N LGNVM array.
LGNVM (Logic Gate Non-Volatile Memory) Introduction