WHOLE NEW NVM TECHNOLOGY
The main application for LGNVM devices is the flash memory array and EEPROM array embedded in digital circuitries fabricated by CMOS logic process. FlashSilicon’s logic process flash memory array is arranged with our proprietary NOR-type cell array architecture for fast random read and optimal programming performance for digital circuitries. The flash array is designed to withstand programming disturbances along the both wordline and bitline up to 1 million programming pulse shots.
Embedded Flash and EEPROM in Digital Circuitries
Fig. 1 shows the cell device threshold voltage distribution for a 1024 x 1024 cell array for programmed cells and erased cells, respectively. Our proprietary low power programming methods only consume ~20 uA per cell in contrast to the conventional Hot Carrier Injection (HCI) of ~100s uA. The low power programming methods inhibit no bitline device punch-through in contrast to the major issue for the convectional HCI method. The semiconductor NVM device punch-through issue has been the major obstacle for scaling down the NOR-type flash array in nano-meter process technology.
Our low power punch-through free programming method (FS-CHISEL) has been applied to the world shortest gate length NVM cell device (50 nm) in the NOR-type flash array. The proprietary sensing scheme for the NOR-type flash array has achieved no DC current sensing in comparison with the conventional current sensing scheme of ~ 100 uA per cell sensing.
The EEPROM array is designed to output the non-volatile memory data in digital signals without utilizing an analog sense amplifier to achieve fast random read access time (< 10 ns). The non-volatile digital data in the embedded EEPROM can be directly fed to a digital circuitry for fast data processing. The unit cell of EEPROM array consists of a pair of complimentary LGNVM devices and one access transistor as shown in Fig. 2.
The non-volatile “bit” is stored by programming one to high threshold voltage state and the other remaining in the low threshold voltage state of the erased complimentary pair LGNVM devices. The digital voltage biases, VDD representing digital value “1” and VSS representing digital value “0”, are applied to the input nodes of the complementary pair NVM devices after programmed. When the control gate of the complementary pair NVM devices is applied with a voltage bias between the “on-threshold” and “off-threshold” voltages the voltage signals at the output node of the complimentary pair is either VDD (“1”) or VSS (“0”). The digital data in the EEPROM cell can be accessed by turning on the access transistor.
LGNVM (Logic Gate Non-Volatile Memory) Introduction