FlashSilicon Inc.   立鴻半導體股份有限公司  |  TEL: +886-3-560-0380  FAX: +886-3-560-0378  Email: sales@flashsilicon.com

 

WHOLE NEW  NVM TECHNOLOGY 

The un-scalable device gate length owing to the device punch-through issue with the conventional CHE (Channel Hot Electron) programming scheme limits the cell size scaling below 90 nm nodes.  FlashSilicon’s new punch-through free programming method is called FS-CHISEL (Floating Source Channel Initiated Secondary Electron) Programming which could effectively solve the conventional Flash memory program punch-through issue.

  Fig. 1  shows no electrical field between source and drain

to create device punch-through leakage current.

The programming sequence is :

1. Floating source electrode.

2. Applying voltage bias VD to drain electrode.

3. Applying voltage pulse VCG to CG for several us.

4. Turn off control gate voltage pulse and drain bias.

  You could refer to our patent for details. (US patent 9082490 B2, CN patent 104240759)

  Fig. 2 shows Flashsilicon implement this technology in 32nm and got a good program window from silicon.

  Fig. 3 and following sequence could  shows you the mechanism of FS-CHISEL.

LGNVM Applications

FS-CHISEL Scheme

 

LGNVM Introduction

 

 

1. Channel diffusion electrons are accelerated in the depleted field toward drain to generate impact ionization

   electron/hole pair near the drain edge.

2. The secondary holes are accelerated downward by the field generated between the applying high control-gate

   voltage and the ground substrate voltage.

3. The accelerated heavy holes transfer their kinetic energies to the light secondary electrons with energy high

   enough to surmount the oxide energy barrier.

 

 

 

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LGNVM (Logic Gate Non-Volatile Memory) Introduction